1. Field of Applicable Technology
The present invention relates to improvements of sense amplifier circuits in a dynamic random access type of semiconductor memory apparatus.
2. Prior Art Technology
In recent years, there has been a considerable increase in the storage capacity and speed of operation that are possible with semiconductor memories, and the field of applications of such memories is rapidly widening. Of the various types of semiconductor memory apparatus, the dynamic random access (abbreviated in the following to DRAM) type of semiconductor memory apparatus has the advantages of a simple circuit configuration and ease of implementation in integrated circuit form, together with a low manufacturing cost. For these reasons the DRAM semiconductor memory apparatus is the main type of memory used to achieve a very large storage capacity. In recent years, technical emphasis has been placed upon achieving DRAMS which have very large storage capacity, together with high speed operation and low power consumption. One of the most important technical point in achieving such a combination of high speed and low power consumption in a large-capacity DRAM is to utilize sense amplifier circuits (for reading out stored data from the memory) which have a high speed of operation and low power consumption. Such sense amplifier circuits must be capable of amplifying the extremely low-level signals that are produced when the memory cells are read, and various techniques have been adopted to achieve this.
A type of sense amplifier circuit that is widely used in the prior art with such a semiconductor memory apparatus will be described in the following, referring to FIG. 1. This is an example of the use of a prior art CMOS type of sense amplifier circuit in a DRAM. Such a circuit is widely employed due to the advantages of a simple circuit arrangement and high operation speed, together with low power consumption. In FIG. 1, the DRAM has 1024 columns of memory cells, with two rows of the memory cells being shown and with columns 3 to 1023 being omitted from the drawing (the rows and columns being oriented respectively vertically and horizontally in the drawing). Respective sense amplifier circuits are provided for each of these columns, with the sense amplifier circuits of the first, second and 1024.sup.th columns being respectively designated by reference numerals 21, 22 and 23, while the circuit further includes a row decoder for executing row selection, and sense amplifier circuit drive circuits The circuit blocks 1 to 6 denote respective memory cells. Of these, the blocks 1 to 3 (each coupled to the word line WL1, in the first, second and 1024.sup.th columns respectively of one row) are respectively made up of a transistor Q13, and a capacitor C1, Q14 and C2, Q15 and C3, while each of the circuit blocks 4, 5 and 6 (each coupled to word line WL2, in the first, second and 1024.sup.th columns respectively of the other row) is identical in configuration to the blocks 1 to 3, with the internal components of blocks 4 to 6 being omitted from the drawing. The sense amplifier circuit 21 of the first column consists of a pair of data lines designated as DL1 and DL1, a pair of p-channel MIS FETs (metal insulation semiconductor field effect transistors) Q1 and Q2 having the source electrodes thereof connected in common and having the drain electrodes and gate electrodes thereof mutually cross-coupled to form a dynamic flip-flop, and also a pair of p-channel MIS FETs Q3 and Q4 having the source electrodes thereof connected in common and having the drain electrodes and gate electrodes thereof mutually cross-coupled to form a dynamic flip-flop. The sense amplifier circuits of the other columns are identical in configuration to sense amplifier circuit 21. In the second column, the pair of data lines are designated as DL2 and DL2, and the sense amplifier circuit transistors as Q5, Q6, Q7 and Q8, while in the 1024.sup.th column, the pair of data lines are designated as DL1024 and DL1024, and the sense amplifier circuit transistors as Q9, Q10, Q11, Q12. A row decoder 7 serves to select one of the word lines WL1 and WL2 in accordance with an address input signal, and activates the selected word line by an activation signal .phi.W. The respective source electrode nodes of the n-channel sides of the 1024 sense amplifier circuits are each connected to a common node SAN, while the source electrode nodes of the p-channel sides of the sense amplifier circuits are each connected to a common node SAP. A p-channel MIS FET Q17 is connected as a switching transistor between the p-channel node SAP and the positive potential V.sub.DD of a power source, while an n-channel MIS FET Q16 is connected similarly between the n-channel node SAN and ground potential (i.e. the 0V potential of the power source). R1 and R2 represent respective lead resistances. A clock signal generating circuit 8 generates the word line activation signal .phi.W, from a reference clock input signal RAS, a clock signal generating circuit 9 generates a clock signal .phi.N that is supplied to the gate electrode of the n-channel MIS FET Q16 as an activation signal for the n-channel flip-flops of the sense amplifier circuits, with .phi.N being derived from the clock signal .phi.W, and a clock signal generating circuit 10 generates a clock signal .phi.P that is applied to the gate electrode of the switching transistor Q17 as an activation signal for the p-channel flip-flops of the sense amplifier circuits, with .phi.P being derived from the clock signal .phi.N.
The operation of the sense amplifier circuit circuits in such a prior art semiconductor memory apparatus will be described in the following.
FIG. 2 shows voltage waveforms at respective nodes in the circuit of FIG. 1. The waveforms illustrate a read operation, for the case in which the word line WL1 is activated (i.e. in which the memory cells 1, 2, 3, are selected) and in which all of the selected memory cells have a data value of logic 0 stored therein. It will be assumed that storage of the data value 0 in a memory cell is represented by the capacitor (e.g. C1, C2 or C3) of the memory cell being charged such that there is a potential difference of V.sub.DD across the capacitor (i.e. the capacitor terminal which is coupled to the transistor of that memory cell is at ground potential). while storage of the data value 1 is represented by the capacitor of the memory cell having zero charge therein (i.e. the capacitor terminal which is connected to the transistor of that memory cell is at the V.sub.DD potential). It will further be assumed that when the reference clock signal RAS is at the non-active level (i.e. in this embodiment, the high logic level), each of the data lines DL1 to DL1024 and the nodes SAP, SAN is maintained at a potential that is one half of the power source voltage V.sub.DD, i.e. these are charged to a preparatory level of V.sub.DD /2. Means for maintaining such a preparatory voltage level in a DRAM are well known in the art, and description will therefore be omitted. The operation will be described in the following referring to FIG. 2. Firstly, at the time point t1, the reference clock input RAS goes to the active level (i.e. the low logic level). Next, at time point t2, .phi.W goes to the active level (the high logic level), and the word line WL1 is activated by the row decoder 7, the transfer gates within the memory cells 1, 2, 3, etc. (i.e. Q13, Q14, Q15) are each set in the conducting condition, and an amount of charge corresponding to the data value 0 is thereby transferred to each of the the data lines DL1, DL2, . . . DL1024. As a result, the respective potentials of each of the data lines DL1 to DL1024 falls slightly, i.e. moves towards ground potential, by an amount .DELTA.V. If for example the stray capacitance of each of the data lines is approximately 10 times the value of capacitance of each memory cell capacitor, then .DELTA.V will be approximately equal to V.sub.DD /20. Next, at time point t3, the signal .phi.n goes to the active level (i.e. the high logic level), the switching transistor Q16 is thereby set in the conducting condition, and the n-channel node SAN begins to be discharged. As this discharging of the n-channel node SAN proceeds, when the difference between the data line of each data line pair that goes to the higher potential of the pair (i.e., in the case of FIG. 2, each of the data lines DL1, . . . ,DL1024) and the potential of the n-channel node SAN rises above the threshold voltage V.sub.TN of the n-channel MIS FETs in the sense amplifier circuits, i.e. at the time point t4, one of the transistors (i.e. Q3, Q7, Q11) of each of the n-channel flip-flops enters the conducting condition. Discharging of the data lines DL1 to DL1024 thereby begins, and amplification operation by the n-channel flip-flop is started. As a result, subsequent to the time point t4, all of the sense amplifier circuits that are connected to the n-channel node SAN are activated (i.e. triggered), and since the load of the switching transistor Q16 now includes 1024 data lines (i.e. one data line of each of the pairs of data lines DL1 to DL1024), the rate of fall of potential of the n-channel node SAN becomes slower than the rate of fall prior to the time point t4. Next, at the time point t5, the p-channel activation signal .phi.P goes to the active level (i.e. the low level), the switching transistor Q17 is set in the conducting condition, and discharging of the p-channel node SAP begins. As will be clear from the fact that the p-channel flip-flops and n-channel flip-flops have a symmetrical circuit configuration, the basic operation of the p-channel flip-flops following the time point t5 will be similar to that of the n-channel flip-flops, with opposite polarities. Specifically, at the time point t6, the potential difference between the data lines DL1 to DL1024 and the p-channel node SAP begins to exceed the threshold voltage V.sub.TP of the p-channel MIS FETs, thereby activating the p-channel MIS FETs, so that charging of the p-channel node SAP begins. Eventually the potential of the data lines DL1 to DL1024 reaches 0V, and the potential of the data lines DL1 to DL1024 reaches the level V.sub.DD. This completes a sense amplifier circuit operation.
Thus with a prior art sense amplifier circuit for a semiconductor memory apparatus, the operation sequence is as follows. Firstly, the n-channel dynamic flip-flops are set in operation. When the amplification has increased to a certain degree, the p-channel dynamic flip-flops are set in operation. The reasons for adopting such a procedure include such factors as the degree of channel surface mobility in each MIS FET, so that an n-channel dynamic flip-flop has a greater amplification factor than a p-channel dynamic flip-flop. Thus, improved performance is achieved if the p-channel flip-flops are actuated after the operation of the n-channel flip-flops has advanced to a certain stage (specifically, to the condition in which a large potential difference has developed between the data lines of each data line pair). That is to say, by ensuring that amplification is started by the n-channel flip-flop of each sense amplifier in response to a voltage difference produced between the data line pair of that sense amplifier, the data thereby generated on the data lines can be made available as rapidly at possible to the next stage, i.e. to a data bus.
However with such a prior art semiconductor memory apparatus in which the the n-channel dynamic flip-flop of each sense amplifier circuit is set in operation prior to the p-channel dynamic flip-flop of the sense amplifier circuit, the following problems arise. Referring to FIG. 3, the operation will be described assuming that read-out is to be executed with the word line WL1 activated, and assuming that memory cell 1 of the selected memory cells stores the data value logic 0 and all of the remaining selected memory cells (2, 3, . . . ) store the data value logic 1. FIG. 3 shows the voltage waveforms at the various nodes for such a case. The time points at which the clock signals RAS, .phi.W, .phi.N, and .phi.P go to their respective active levels are identical to those of FIG. 2 described above, i.e. the time points t1, t2, t3 and t5. At t2, the word line activation signal .phi.W goes to the active level, whereby the word line WL1 is activated. Since charge is thereby transferred from the memory cells 1, 2, 3 to the data lines DL1, DL2, . . . DL1024, and since as described above the memory cell 1 stores the data value 0, the potential of the data line DL1 will fall by the amount .DELTA.V, while since the other memory cells each have the data value 1 stored therein, each of the data lines DL2 to DL1024 will increase in potential by the amount .DELTA.V. At the time point t3, the n-channel activation signal .phi.N goes to the active level, and the switching transistor Q16 is thereby set in the conducting condition, whereby the potential of the n-channel node SAN falls. Thereafter, the potential difference between each of the high-potential data lines DL2 to DL1024 and the n-channel node SAN rises above the n-channel MIS FET threshold voltage V.sub.TN (at time point t4'). Amplification by the respective n-channel flip-flops corresponding to the data lines DL2 to DL1024 begins, so that discharging of the data lines DL2 to DL1024 begins, At the time point t4', the n-channel flip-flop corresponding to the data line DL1 is not activated, since at that time the potential difference between the data line DL1 and the n-channel node SAN is lower than V.sub.TN. Discharging of the n-channel node SAN proceeds, and at the time point t4" (i.e. the point at which the potential difference between the data line DL1 and the n-channel node SAN reaches the value V.sub.TN) the n-channel MIS FET Q3 of the sense amplifier circuit 21 is set in the conducting condition, so that the n-channel flip-flop of the sense amplifier circuit 21 is activated, and amplification of the DL1 potential begins.
As can be seen from FIG. 3, there is a substantial difference between the time points at which respective sense amplifier circuits are activated in such a case, with a prior art DRAM dma. As a result of very small differences between the data line potentials at the time point when the signal .phi.N goes to the active level (i.e. the potential .DELTA.V, in the case of FIG. 3, between each of the data lines DL2 to DL1024 and the data line DL1), a difference arises between the respective time points at which amplification by the n-channel flip-flops begins. The slower the rate of fall of potential of the n-channel node SAN, following the time point t4', the greater will become such a difference between the times at which amplification by the n-channel flip-flops begins. In the case of FIG. 3, since the memory condition is assumed in which data value 0 is stored only the memory cell 1 and each of the memory cells 2 to 1024 has the data value 1 stored therein, the majority of the sense amplifier circuits that are connected in common to the n-channel node SAN will be activated at the time point t4'. Since the load of the switching transistor Q16 then becomes high (i.e. since a large number of data lines, and hence a large value of capacitance, must now be discharged by the current flow through that transistor), the rate of fall of potential of the n-channel node SAN will be significantly lower than was the case prior to the time point t4'. Thus in such a case, the start of operation of the sense amplifier circuit that is connected to the data line pair DL1, DL1 will be considerably delayed by comparison with the other sense amplifier circuits.
A similar problem arises in the activation timings of the p-channel flip-flops of the sense amplifiers. In the example of FIG. 3, at the time point t5 when the potential rise of the p-channel node SAP begins, since the potential of each of the data lines DL2 to DL1024 is lower than that of the data line DL1, the p-channel flip-flops that correspond to the data lines DL2 to DL1024 will each be activated first (at time point t6'), while the start of operation of the p-channel flip-flop that corresponds to the data line DL1 will be delayed (i.e. starting at time point t6").
In this way, when the prior art configuration of FIG. 1 is utilized, then when the majority of the memory cells of a selected word line have the data value 1 stored therein, the remaining memory cells, which store the value 0, will exhibit a substantial delay in the start of sense amplifier circuit operation. That problem becomes especially severe in the case of a semiconductor memory apparatus having a very large storage capacity, since in that case the value of lead resistance through which current must flow in order to discharge the data lines (i.e. the values R1, R2 in FIG. 3, and the total amount of data line capacitance that must be discharged, will both be accordingly large.